Design of a CMOS delay generator for RF UWB and time-domain systems

A novel programmable high-precision delay generator with adjustable digital control for ultra-wideband and time-domain RF applications was designed. Ring oscillator based phase locked loop (PLL) is embedded to achieve desired propagation delay in the delay cell against process, temperature and power supply variations. A replica inverter delay line parallel to the PLL offers a separate delay path for input clock. Sub-nanosecond delay step with high accuracy can be obtained by shaping the input clock slope and keeping a careful matching between the replica delay line and the delay cell in PLL. The prototype of the delay generator is implemented on a 0.18-μm CMOS process. The measurement results show relative delay error of 0.8%. The circuit consumes 9.5 mA from a 1.8-V power supply.