Reduction of the stray inductance in a switching cell using the Power Chip-On-Chip 3D integration concept

With the emergence of new power semiconductor devices, the switching speeds are increasing. The stray inductance of switching cells must be minimised to limit the over-voltage of power switches like IGBTs, MOSFETs or HEMTs. This is one of the reasons why 3D integration concepts are considered today. This paper deals with a busbar-like integration concept called “Power Chip-on-Chip” (PCoC). Although this concept can improve the electrical and EMI behaviours of power converters, the heat extraction is an important issue. A parametric study using an impedance analyser is conducted to study the influence of the cooling system on the stray inductance value. An experimental set-up is then outlined to validate the preliminary study. We demonstrate that the stray inductance (and thus the over-voltage) of a PCoC package is lower than this of a planar power module using the same components.