ViDL: A Versatile ISA Description Language

Application specific processors as part of systems-on-a-chip (SoCs) have become increasingly popular in recent years. The need for efficient development of such processors raises the demand for simple and reliable tools and respective specification languages. This paper presents the Versatile Instruction Set Architecture Description Language (ViDL), to formally define (application specific) instruction sets. Simulators and processor implementations are then generated from such specifications. The language features functional and domain specific concepts to allow for rapid and simple specification of realistic instruction sets. In contrast to related approaches, ViDL strictly abstracts from micro architectural aspects, such as the instruction pipeline and hazard resolution. These aspects are shifted from the developer to a generator, which greatly simplifies specification and increases reliability. From the very same ViDL specification, we can automatically generate consistent instruction set simulators (40 - 140 MIPS), web-based simulators, and a set of processors with different pipeline structures (2-7 stages, 300-650 MHz). Formalization of instruction sets (ARM, MIPS, Power, SRC, and Core VA) in ViDL has shown to be simple. It took only between 2 month and 90 minutes.