A Module for Automatic Assessment and Verification of Students´ Work in Digital Logic Design

The paper describes the Verification Module for automatic assessment and verification of students´ work in digital logic design. The Verification Module has been developed and used at the School of Electrical Engineering, University of Belgrade as part of a system for digital logic design and simulation, which also includes the Synthesis Module and the Simulation Module. The Synthesis Module and the Simulation Module allow students preparing for the exam in digital logic design first to verify the correctness of each step of the formal design process and then to draw and simulate their own design. The Verification Module makes it possible to teachers to automate the verification and assessment of student´s work at the exam. The task given to students at the exam is to carry out the synthesis of a switching circuit on paper, draw and simulate its structural scheme using the Simulation Module and submit the final design for assessment. Teachers use the Synthesis Module to obtain the solution for the task given to students. The Verification Module compares solutions submitted by students with the one obtained by the Synthesis Module and assigns points in accordance with the algorithm for the assessment of students work. The paper presents the algorithm adopted together with basic elements of its implementation and gives typical examples of its usage.