A high-speed power and resolution adaptive flash analog-to-digital converter

Author

Nahata, S. ; Choi, Kyusun ; Yoo, Jincheol

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

fYear

2004

fDate

12-15 Sept. 2004

Firstpage

33

Lastpage

36

Abstract

A high-speed and small-area power and resolution adaptive flash ADC is presented. The high-speed power and resolution adaptive ADC (HSPRA-ADC) utilizes an encoder design which significantly improves its speed and minimizes the chip area over the earlier design. Moreover, the ADC also achieves lower power consumption compared to the earlier design. The HSPRA-ADC enables exponential power reduction with linear resolution reduction. The unused parallel voltage comparators are switched to the standby mode during which they consume only the leakage power. The HSPRA-ADC was designed and simulated using 0.18 μm and 0.07 μm CMOS technologies. The HSPRA-ADC is desirable in wireless mobile applications.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); high-speed integrated circuits; integrated circuit design; low-power electronics; 0.07 micron; 0.18 micron; CMOS technologies; HSPRA-ADC; analog-to-digital converter; encoder design; exponential power reduction; flash ADC; high-speed power and resolution adaptive ADC; leakage power; linear resolution reduction; parallel voltage comparators; power consumption; standby mode; wireless mobile applications; Analog-digital conversion; Binary codes; CMOS technology; Computer science; Energy consumption; Inverters; Power engineering and energy; Read only memory; Signal resolution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2004. Proceedings. IEEE International

Print_ISBN

0-7803-8445-8

Type

conf

DOI

10.1109/SOCC.2004.1362342

Filename

1362342