Superior nMOSFET scalability using Fluorineine co-implantation and spike annealing

Author

Kubicek, S. ; Hoffmann, T. ; Augendre, E. ; Pawlak, B. ; Chiarella, T. ; Kerner, C. ; Severi, S. ; Falepin, A. ; De Keersgieter, A. ; Noda, T. ; Jurczak, M. ; Absil, P. ; Biesemans, S.

Author_Institution

IMEC, Leuven

fYear

2006

fDate

Oct. 2006

Firstpage

101

Lastpage

104

Abstract

The paper reports the simultaneous improvement of both on- and off-properties for nMOSFETs by means of fluorineine co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with fluorineine co-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted and C co-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (R_EXT) vs. effective channel length (Leff) trade-off are examined

Keywords

MOSFET; annealing; ion implantation; deca-nanometric range; drain-induced barrier lowering; effective channel length; external resistance; fluorineine coimplantation method; nMOSFET scalability; source-drain extensions; spike annealing; threshold current; Annealing; Atomic beams; Conductivity; Dielectric devices; Fabrication; Gate leakage; Implants; Leakage current; MOSFET circuits; Scalability;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Devices and Microsystems, 2006. ASDAM '06. International Conference on

Conference_Location

Smolenice Castle

Print_ISBN

1-4244-0369-0

Type

conf

DOI

10.1109/ASDAM.2006.331164

Filename

4133088