Title :
Clock tree tuning using shortest paths polygon
Author :
Saaied, Haydar ; Al-Khalili, Dhamin ; Al-Khalili, Asim J.
Author_Institution :
Concordia Univ., Montreal, Que., Canada
Abstract :
A model to facilitate a better routing of a multiterminal net under obstacle constraints is presented. The model is applied to the clock tree routing problem. Using this model, in conjunction with simple routines, all possible locations of a Steiner node in the routing plane are determined. As a result, less wire length is achieved compared to other methods. The model has been incorporated in a local modification algorithm to efficiently implement engineering change orders (ECOs) of clock trees.
Keywords :
clocks; integrated circuit interconnections; integrated circuit modelling; network routing; Steiner node; clock tree tuning; engineering change orders; multiterminal net routing; obstacle constraints; shortest paths polygon; Bismuth; Clocks; Routing; Solids; Wire;
Conference_Titel :
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN :
0-7803-8445-8
DOI :
10.1109/SOCC.2004.1362350