2008398

Process Integration for a 2ns Cycle/4ns Access 512K CMOS SRAM

Joshi, R. ; Klepner, S. ; Basavaiah, S. ; Ray, A. ; Petrillo, K. ; Mazzeo, N. ; Bucelot, T. ; Brodsky, S. ; Jaso, M. ; Brunner, T. ; Petrillo, E. ; Stein, K. ; Lii, T. ; Franch, R. ; Chappell, B. ; Chappell, T. ; Schuster, S.

IBM Research Division, New York

1991

28-30 May 1991

31

32

CMOS process; CMOS technology; Circuits; Delay; Etching; Fabrication; Lenses; Random access memory; Silicides; Wiring;

English

ieee

VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on

Oiso, Japan

conf

10.1109/VLSIT.1991.705975

705975