Title :
Leakage aware SER reduction technique for UDSM logic circuits
Author :
Elakkumanan, Praveen ; Ananthakrishnan, Vishwanath ; Narasimhan, Ashok ; Sridhar, Ramalingam
Author_Institution :
Dept. of Comput. Sci. & Eng., Buffalo Univ., NY, USA
Abstract :
With technology scaling aggressively into the very deep submicron era, leakage power and single event upsets (SEUs) pose serious challenges to circuit designers. Here, we present a technique to reduce the soft error rate (SER) in combinational circuits, with minimal area overhead using minimum leakage input vector (MLIV) leakage reduction technique. Simulation results show significant reduction in area overhead as compared to existing techniques, while reducing the leakage power by nearly 40%.
Keywords :
combinational circuits; integrated circuit design; integrated circuit reliability; leakage currents; logic design; SER reduction; UDSM logic circuits; combinational circuits; integrated circuit reliability; leakage power; leakage reduction; minimum leakage input vector; single event upsets; soft error rate; ultradeep submicron design; Circuit simulation; Combinational circuits; Computer science; Coupling circuits; Error correction; Logic circuits; Protection; Single event transient; Single event upset; Voltage;
Conference_Titel :
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN :
0-7803-8445-8
DOI :
10.1109/SOCC.2004.1362357
