Asynchronous timing recovery for passband PS-FSE for single-chip V.32 modems

In single chip V.32 modems (full duplex) there are two clocks that must be synchronized: the near-end and the far-end clock. However, a single chip implementation has only a single clock. In the present design the transmit data is generated and echoes cancelled synchronously using the near-end clock. Far-end data is generated from the far-end clock and thus for successful demodulation the far-end samples must be interpolated to the correct timing epochs for near-end detection and as such are asynchronous with the near-end (chip) clock. The authors employ an all-pass interpolation, low pass filter in this role and their research represents the first application of adaptive, asynchronous timing recovery to a receiver containing an adaptive equalizer. Such filters have previously (Park, 1991) been used in sample rate conversion in audio signal processing applications. The present data detection algorithms use a passband, phase-splitting, fractionally spaced equalizer (PS-FSE) with adaptive carrier recovery (Funderburk and McLean, 1992). The algorithm for timing error measurement uses a well known method based on the equalizer tap-gains to develop an error signal for adaptive, asynchronous timing recovery and sample-rate conversion. However, its application to a PS-FSE is new. Also, the present algorithm involves polyphase interpolation filters and the required rate conversion if the near-end clock is relatively faster or slower than the far-end clock. Performance is demonstrated using computer simulation and a real-time, DSP based experiment that uses a telephone network simulator