Title :
Silencer!: a tool for substrate noise coupling analysis
Author :
Birrer, Patrick ; Fiez, Terri S. ; Mayaram, Kartikeya
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Abstract :
Silencer! is a new, fully automated, substrate noise coupling analysis tool that is integrated into the CADENCE DFII design environment. This tool seamlessly enables substrate noise coupling analysis in a standard mixed-signal design flow. IC designers can analyze substrate noise coupling at different levels of hierarchy - from the schematic level to the layout. Examples have been simulated and the results are accurate to within 10% of measured fabricated chips.
Keywords :
circuit CAD; integrated circuit design; integrated circuit noise; mixed analogue-digital integrated circuits; substrates; CADENCE DFII design environment; IC design; Silencer!; mixed signal integrated circuits; mixed-signal design; substrate noise coupling analysis; system-on-chip; Analytical models; Circuit noise; Coupling circuits; Data mining; Integrated circuit interconnections; Integrated circuit noise; Noise generators; Power supplies; Radio frequency; Working environment noise;
Conference_Titel :
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN :
0-7803-8445-8
DOI :
10.1109/SOCC.2004.1362367
