A low power architecture for digital sequence generation

The conventional implementation of digital sequence generators suffers from two major drawbacks: (1) it generates only one bit per clock cycle and, (2) all the elements in the structure are clocked every clock cycle. Sequences implemented using this architecture will dissipate a significant amount of power when clocked at high frequency rate. This is detrimental to the operation of low-power communication equipment and other battery operated systems. This paper presents an architecture and an algorithm for the parallel implementation of digital sequences and digital systems in general. The advantages of the presented architecture are: (1) higher throughput rate and (2) reduced power dissipation which is much less dependent on the length of the shift register. This technique is applicable to most digital systems requiring low-power operation