DocumentCode
2008937
Title
A scalable and robust rail-to-rail delay cell for DLLs
Author
Bengtson, Håkan ; Svensson, Christer
Author_Institution
Dept. of Electr. Eng., Linkoping Universitet, Sweden
fYear
2004
fDate
12-15 Sept. 2004
Firstpage
135
Lastpage
136
Abstract
This paper describes a scalable and robust differential rail-to-rail delay cell. The delay cell is fabricated in a 3.3 V 0.35 μm CMOS process. The delay cell shows a wide-range operation and low power supply sensitivity. The delay range is 0.31 ps to 21.8 ns. For 0.5 ns delay, when the clock period is 500 MHz, the power supply sensitivity is 0.033 ps/mV. The delay cell is used in a DLL for clock generation of a four times interleaved 2 Gb/s decision feedback equalizer.
Keywords
CMOS analogue integrated circuits; delay lock loops; delay-differential systems; delays; low-power electronics; 0.31E-12 to 21.8E-9 s; 0.35 micron; 0.5 ns; 3.3 V; 500 MHz; CMOS; DLL; differential rail-to-rail delay cell; low power supply sensitivity; Clocks; Decision feedback equalizers; Delay lines; Diodes; Jitter; MOSFETs; Power supplies; Resistors; Robustness; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN
0-7803-8445-8
Type
conf
DOI
10.1109/SOCC.2004.1362378
Filename
1362378
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