DocumentCode
2009111
Title
A novel phase detector for PAM-4 clock recovery in high speed serial links
Author
Lim, Kahn Li ; Zilic, Zeljko
Author_Institution
Microelectron. & Comput. Syst. Lab., McGill Univ., Montreal, Que., Canada
fYear
2004
fDate
12-15 Sept. 2004
Firstpage
151
Lastpage
152
Abstract
This paper presents a new method for multilevel clock recovery for high speed serial links. This all-digital implementation requires little overhead and no special encoding of data streams is required. A high speed 2-bit ADC is designed and presented for clock recovery purpose.
Keywords
analogue-digital conversion; clocks; phase locked loops; ADC circuit; PAM-4 clock recovery; high speed comparator; high speed serial links; multilevel clock recovery; phase detector; phase lock loops; Clocks; Detectors; Dielectric losses; Encoding; Logic; Phase detection; Propagation losses; Reflection; Signal detection; Skin effect;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN
0-7803-8445-8
Type
conf
DOI
10.1109/SOCC.2004.1362386
Filename
1362386
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