CVD-cobalt for low resistance word line electrode of 3D NAND flash memory

This paper presents an optimized Co silicide process to realize low resistance multilayered word lines in 3D NAND Flash device. With CVD Co method, it is obtained that the step coverage is about 97% at the aspect ratio of 15:1 trench. Co silicide is successfully formed using in-situ 1^st anneal without capping metal on it. It is demonstrated that the resistivity of CVD Co silicide is very close to the PVD Co silicide, and the thermal stability is also comparable up to 900°C. We also investigate fundamental material properties; Co/Si ratio, interlayer thickness, surface roughness and the dominant process conditions related to silicide growth. As a result of step coverage, resistivity, and thermal stability, it is suggested that CVD Co is suitable for forming Co silicide word line of 3D NAND flash memory.