CVD-cobalt for low resistance word line electrode of 3D NAND flash memory

Author

Kim, MinSoo ; Whang, SungJin ; Lee, YoungJin ; Han, JooHee ; Choi, JinHae ; Lee, ByoungHo ; Sheen, Dongsun ; Pyi, Seungho ; Kim, Jinwoong

Author_Institution

R&D Div., Hynix Semicond. Inc., Icheon, South Korea

fYear

2011

fDate

8-12 May 2011

Firstpage

1

Lastpage

3

Abstract

This paper presents an optimized Co silicide process to realize low resistance multilayered word lines in 3D NAND Flash device. With CVD Co method, it is obtained that the step coverage is about 97% at the aspect ratio of 15:1 trench. Co silicide is successfully formed using in-situ 1^st anneal without capping metal on it. It is demonstrated that the resistivity of CVD Co silicide is very close to the PVD Co silicide, and the thermal stability is also comparable up to 900°C. We also investigate fundamental material properties; Co/Si ratio, interlayer thickness, surface roughness and the dominant process conditions related to silicide growth. As a result of step coverage, resistivity, and thermal stability, it is suggested that CVD Co is suitable for forming Co silicide word line of 3D NAND flash memory.

Keywords

NAND circuits; chemical vapour deposition; cobalt; flash memories; surface roughness; thermal stability; three-dimensional integrated circuits; 3D NAND flash memory; CVD; chemical vapour deposition; interlayer thickness; low resistance word line electrode; resistivity; step coverage; surface roughness; temperature 900 C; thermal stability; Annealing; Conductivity; Films; Silicides; Silicon; Thermal stability; Three dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International

Conference_Location

Dresden

ISSN

pending

Print_ISBN

978-1-4577-0503-8

Type

conf

DOI

10.1109/IITC.2011.5940281

Filename

5940281