Title :
Aspects of chip/package interaction and 3-D integration assessed by the investigation of crack and damage phenomena in low-k BEoL stacks
Author :
Auersperg, Jürgen ; Rzepka, Sven ; Michel, Bernd
Author_Institution :
Micro Mater. Center, Fraunhofer ENAS, Chemnitz, Germany
Abstract :
Miniaturization and increasing functional integration push the development of feature sizes of advanced CMOS down to the nanometer range. New low-k and ultra low-k materials in Back-end of line (BEoL) structures cause new challenges for reliability analysis and prediction, in addition. A combined numerical/experimental approach will be explained towards optimizing fracture and fatigue resistance of BEoL-structures by making use of bulk and interface fracture concepts. The risk of near-chip-edge and near-bump cracking in BEoL-structures with lead-free as well as copper-pillar interconnects is analyzed and optimized under chip package interaction (CPI) and FC-reflow-soldering, in particular.
Keywords :
CMOS integrated circuits; crack detection; failure analysis; fracture; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; low-k dielectric thin films; reflow soldering; three-dimensional integrated circuits; 3D integration; Backend of line structure; CMOS; FC reflow soldering; chip package interaction; chip/package interaction; copper pillar interconnects; crack investigation; damage investigation; fatigue resistance; fracture resistance; functional integration; interface fracture; low-k BEoL stacks; near bump cracking; near chip edge; Copper; Delamination; Materials; Reliability; Residual stresses; Stress measurement;
Conference_Titel :
Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-0503-8
DOI :
10.1109/IITC.2011.5940283
