A novel approach to the design and implementation of very high-speed digit-serial modified-Booth multipliers

A novel approach is presented for the design and implementation of very high-speed digit-serial modified-Booth multipliers. In this approach, the partial product sum components are represented in their signed-binary (SB) format while the corresponding intermediate partial product components are represented in their two´s complement (TC) format to permit very high-speed carry/borrow free multiplication. The full-precision SB product is made to undergo IEEE Standard 754 rounding. The proposed modified-Booth multipliers permit very high throughputs for arbitrary values of digit size, are highly area-time efficient for large digit sizes, and lead to uniform implementations with highly localized interconnections making them suitable for VLSI. These multipliers are verified using Viewlogic simulations for a corresponding Actel 1.2 μ FPGA technology implementation