Title :
A low clock load conditional flip-flop
Author :
Hansson, Martin ; Alvandpour, Atila
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
Abstract :
We describe a low clock load conditional transmission-gate flip-flop aimed at reducing on-chip clock power consumption. It utilizes a scalable and simple leakage compensation technique, which injects additional leakage current in opposite direction, thus compensating for the worst-case leakage. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. Post-layout simulations show a 30 % clock power reduction compared to a conventional static flip-flop.
Keywords :
circuit layout; flip-flops; leakage currents; power consumption; timing circuits; clock power reduction; leakage compensation; leakage current; low clock load conditional flip-flop; on-chip clock power consumption reduction; post-layout simulation; transmission-gate flip-flop; CMOS technology; Clocks; Delay; Energy consumption; Flip-flops; Inverters; Latches; Leakage current; Robustness; Very large scale integration;
Conference_Titel :
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN :
0-7803-8445-8
DOI :
10.1109/SOCC.2004.1362394
