Achieving higher dynamic range in flash A/D converters

This paper proposes a robust, fault-tolerant scheme to achieve high spurious free dynamic range (SFDR) in an averaging flash A/D converter using comparator chopping. Chopping of all comparators using a novel array of truly binary random number generators is proposed. Chopping randomizes the residual offset left after averaging, further pushing the dynamic range of the converter. Power consumption and area are reduced because of the relaxed design requirements for the same linearity. The technique has been verified for a 6-bit 1Gsample/s flash ADC under case of process gradients with nonzero mean offsets as high as 60m V and potentially serious spot offset errors as high as 1V for a 2V peak to peak input signal. The proposed technique exhibits an improvement of over 15dB compared to pure averaging flash converters for all cases.