DocumentCode
2009630
Title
Yield improvement and ramp-up to production of advanced CMOS technologies interconnects
Author
Gonella, Roberto
Author_Institution
STMicroelectronics, Crolles, France
fYear
2011
fDate
8-12 May 2011
Firstpage
1
Lastpage
3
Abstract
Process complexity of advanced CMOS technologies interconnect increases continuously in the uninterrupted move towards miniaturization and verticalization. In the same time the window market of new more complex consumer products are shrinking faster and faster. This paper gives a comprehensive description of the most relevant and advanced methodologies and tools carried out to achieve quickly a yielding and reliable BEOL interconnect process in most advanced technologies.
Keywords
CMOS integrated circuits; integrated circuit yield; semiconductor device metallisation; BEOL interconnect process; advanced CMOS technologies interconnects; yield improvement; Calibration; Failure analysis; Integrated circuits; Layout; Metals; Sensitivity; Systematics;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International
Conference_Location
Dresden
ISSN
pending
Print_ISBN
978-1-4577-0503-8
Type
conf
DOI
10.1109/IITC.2011.5940303
Filename
5940303
Link To Document