Title :
Built-in test methodology for a full custom processor chip
Author :
Shergill, Ravinder S. ; Yeung, Pak-Ho ; Tucci, Patrick A.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
A description is given of a comprehensive built-in test approach followed in the design of a dedicated 32-b CMOS VLSI data processor chip. The approach is comprehensive in nature. All aspects of chip verification are addressed, including limited self-checking during normal operation, complete testability during production testing through full scan-path implementation on all system latches, facilitation of board level in-circuit testing through provisions of boundary scan, built-in self-test, and a test bus port that is compatible with the emerging JTAG/IEEE standards. A method used to facilitate maximum operating frequency testing is outlined
Keywords :
CMOS integrated circuits; VLSI; automatic testing; integrated circuit testing; JTAG/IEEE standards; board level in-circuit testing; boundary scan; built-in self-test; chip verification; complete testability; dedicated 32-b CMOS VLSI data processor chip; full custom processor chip; full scan-path implementation; limited self-checking; maximum operating frequency testing; normal operation; production testing; system latches; test bus port; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer aided manufacturing; Engines; Semiconductor device modeling; Space technology; System testing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63430
