DocumentCode :
2009770
Title :
SRAM word-oriented redundancy methodology using built in self-repair
Author :
Lee, Jihyun ; Lee, Young Jun ; Kim, Yong Bin
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fYear :
2004
fDate :
12-15 Sept. 2004
Firstpage :
219
Lastpage :
222
Abstract :
In this paper, a word-oriented built in self-repair (BISR) technique for SRAM bank is presented. All the repairs using BISR circuit are done during the reset period, and the process of referencing to the faulty line and its redundancy address are not required during the normal operation. The access time penalty is negligible and additional power consumption due to BISR circuit is kept minimum since it operates only during the reset time. Flexibility of this design technique allows to repair more numbers of faulty lines than conventional approaches with less area overhead.
Keywords :
SRAM chips; built-in self test; fault tolerance; redundancy; BISR circuit; SRAM bank; built in self-repair; faulty line referencing; reset period; word-oriented redundancy; CADCAM; Circuit faults; Computer aided manufacturing; Energy consumption; Fuses; Logic; Random access memory; Redundancy; Shift registers; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN :
0-7803-8445-8
Type :
conf
DOI :
10.1109/SOCC.2004.1362414
Filename :
1362414
Link To Document :
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