On-chip network based embedded core testing

In this paper, network-based embedded core testing (NET) architecture is proposed. The test of individual embedded cores and their interconnection are possible in a system-on-chip (SoC) environment by using configurable on-chip network (OCN) architecture. And the test time can be reduced because the proposed test access mechanism provides high bandwidth for test patterns transport. In addition, since the core access path during test shares with the communication architecture of the SoC, the area overhead can be reduced. A network-on-chip (NoC) application with the proposed NET architecture is implemented. The operation and the performance of NET architecture are described.