Title :
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
Author :
Lan, Ying-Cherng ; Lo, Shih-Hsin ; Lin, Yueh-Chi ; Hu, Yu-Hen ; Chen, Sao-Jie
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate at each on-chip router. In this paper, a novel on-chip router architecture supporting the self-configuring bidirectional channel mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulation runs on this BiNoC network under synthetic and real-world traffic patterns demonstrate consistent and significant performance advantage over conventional mesh grid NoC architecture equipped with hard-wired unidirectional channels.
Keywords :
network-on-chip; reconfigurable architectures; bandwidth utilization; bidirectional NoC architecture; dynamic self-reconfigurable channel; hard-wired unidirectional channels; mesh grid NoC architecture; on-chip communication; on-chip router architecture; packet delivery latency; self-configuring bidirectional channel mechanism; Bandwidth; Communication channels; Communication system control; Computer architecture; Hardware; Logic; Network-on-a-chip; Spine; Telecommunication traffic; Traffic control; NoC; bidirectional channel;
Conference_Titel :
Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
978-1-4244-4142-6
Electronic_ISBN :
978-1-4244-4143-3
DOI :
10.1109/NOCS.2009.5071476