Title :
Low damage etch approach for next generation Cu interconnect
Author :
Singh, Sunil K. ; Lee, C.J. ; Tsai, C.H. ; Huang, T.M. ; Lu, C.W. ; Tsai, T.J. ; Chang, Y.S. ; Bao, T.I. ; Shue, S.L. ; Yu, C.H.
Author_Institution :
Exp Interconnect Module Dept., Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
This research focus on low radical plasma etch (LRPE) process and its impact on highly porous dielectric material (extreme-low-k, ELK, k=2.4). We demonstrate a dual damascene (DD) process flow without k degration by low radical and pore sealing plasma etch. Comparing to tranditional DD etching process, 12% resistance-capacitance (RC) improvement, 15% via resistance reduction and a factor of 3 inter-metal-dielectric (IMD) time dependent dielectic breakdown (TDDB) improvement can be achieved by the proposed approach.
Keywords :
copper; dielectric materials; integrated circuit interconnections; sputter etching; Cu; dual damascene process flow; highly porous dielectric material; inter-metal-dielectric time dependent dielectic breakdown; low damage etch approach; low radical plasma etch process; next generation interconnect; resistance reduction; resistance-capacitance improvement; Carbon; Etching; Films; Metals; Oxygen; Plasmas; Resistance;
Conference_Titel :
Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-0503-8
DOI :
10.1109/IITC.2011.5940313
