Title :
Multilevel interconnect networks for the end of the roadmap: Conventional Cu/low-k and emerging carbon based interconnects
Author :
Ceyhan, Ahmet ; Naeemi, Azad
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
The impact of size effects such as surface and grain boundary scatterings and line edge roughness (LER) on the design of a multi-level interconnection network, and potential power saving offered by individual single-wall nanotube (SWNT) and mono-layer graphene interconnects are investigated and quantified for high-performance and low-cost designs implemented at future technology nodes. It is shown that size effects increase the number of metal levels for a high performance chip by as large as 22.81% and 41.35% at the 21nm and 7.5nm technology nodes, respectively. It has also been demonstrated that individual metallic SWNT and mono-layer graphene interconnects may be used to reduce the interconnect power dissipation in both high-performance and low-cost designs at the end of the roadmap. This is in contrast to previous publications which all indicated that bundles of densely packed SWNTs are needed for interconnect applications.
Keywords :
copper; graphene; integrated circuit interconnections; nanotubes; surface scattering; Cu; carbon based interconnects; copper interconnects; grain boundary scatterings; high performance designs; interconnect power dissipation; line edge roughness; low cost designs; low-k interconnects; monolayer graphene interconnects; multilevel interconnect networks; single wall nanotube; size 21 nm; size 7.5 nm; size effects; surface scatterings; Capacitance; Copper; Integrated circuit interconnections; Power dissipation; Resistance; Wires;
Conference_Titel :
Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International
Conference_Location :
Dresden
Print_ISBN :
978-1-4577-0503-8
DOI :
10.1109/IITC.2011.5940314
