Title :
Performance analysis of implement-oriented capacity-achieving LDPC codes on erasure channel and its encoder design
Author :
Peng, Li ; Zhu, Guangxi ; Luo, Qi
Author_Institution :
Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China
Abstract :
This paper is concerned with threshold performance analysis of implement-oriented low-density parity check (LDPC) ensemble on binary erasure channel and design of its H-matrix structure and encoder hardware architecture. We construct a class of the special LDPC ensemble which has capacity-achieving degree distribution pair for infinity length code over the binary erasure channel (BEC). Its special characteristic different from the other LDPC ensembles is that the coefficient lambda1 of its degree distribution pair equal 1 instead of 0. Its H-matrix is constructed by combining zigzag matrix and partitioned permutation matrices. This paper completed a design from capacity-achieving sequence to algebraic structural H-matrix, and the H-matrix can directly be used to design low complexity recursive encoding circuit.
Keywords :
channel coding; matrix algebra; parity check codes; random codes; BEC; algebraic structural H-matrix; binary erasure channel; capacity-achieving degree distribution pair; encoder hardware architecture design; implement-oriented LDPC code; infinity length code; low complexity recursive encoding circuit design; low-density parity check code; permutation matrix partition; random code; zigzag matrix; Algorithm design and analysis; Circuits; Design engineering; Error probability; H infinity control; Hardware; Linear code; Paper technology; Parity check codes; Performance analysis; Binary erasure probability; Density evolution; Low-density parity-check (LDPC) codes; Thresholds; encoding circuit; recursive encoder;
Conference_Titel :
Global Mobile Congress 2009
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5302-3
Electronic_ISBN :
978-1-4244-5301-6
DOI :
10.1109/GMC.2009.5295824