A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders

Author

Wieckowski, Michael ; Margala, Martin

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

fYear

2004

fDate

12-15 Sept. 2004

Firstpage

251

Lastpage

254

Abstract

The proposed design demonstrates a new high-speed, low-power methodology in a 32 Kb SRAM cache. A fast cycle time of up to 3 GHz is accomplished by using pipelined asynchronous decoders along with a parallel local/global decoding scheme. Power consumption is minimized by using current mode reads and writes throughout the design. The resulting cache operates with an average power dissipation of 390mW at 2GHz in 1.8V, 0.18μm bulk CMOS technology.

Keywords

CMOS integrated circuits; SRAM chips; cache storage; current-mode circuits; integrated circuit design; low-power electronics; 0.18 micron; 1.8 V; 2 GHz; 3 GHz; 32 Kbit; 390 mW; SRAM cache; asynchronous wave-pipelined decoders; bulk CMOS technology; current mode operation; current mode reads; current mode writes; parallel global decoding; parallel local decoding; pipelined asynchronous decoders; power consumption; power dissipation; CMOS technology; Decoding; Energy consumption; Modems; Operational amplifiers; Power dissipation; Pulse amplifiers; Pulse generation; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2004. Proceedings. IEEE International

Print_ISBN

0-7803-8445-8

Type

conf

DOI

10.1109/SOCC.2004.1362425

Filename

1362425

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2010018