Title :
A weighted fair queuing finishing tag computation architecture and implementation
Author :
McKillen, Colm ; Sezer, Sakir
Abstract :
This paper investigates a customized implementation for Xilinx Virtex Pro board of a weighted fair queuing (WFQ) tag scheduler that has the capacity to serve 8,000 individual sessions at over 100MHz. The implementation is actually capable of handling up to 64,000 different sessions requiring only the use of a minimal size FPGA. This represents an excellent hardware cost for a next generation terabit router.
Keywords :
field programmable gate arrays; packet switching; processor scheduling; queueing theory; reconfigurable architectures; 100 MHz; FPGA; WFQ tag scheduler; Xilinx Virtex Pro board; finishing tag computation; network processing; reconfigurable architectures; scheduling; terabit router; weighted fair queuing; Bandwidth; Computer architecture; Concurrent computing; Delay; Finishing; Global Positioning System; Processor scheduling; Quality of service; Round robin; Technical Activities Guide -TAG;
Conference_Titel :
SOC Conference, 2004. Proceedings. IEEE International
Print_ISBN :
0-7803-8445-8
DOI :
10.1109/SOCC.2004.1362431
