A study of TSV variation impact on power supply noise

Author

Jung, Moongon ; Panth, Shreepad ; Lim, Sung Kyu

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2011

fDate

8-12 May 2011

Firstpage

1

Lastpage

3

Abstract

In this work, we study the through-silicon-via (TSV) RC variation impact on 3D power delivery network (PDN). First, we model TSV RC variation due to process variation. Then, we perform sign-off power supply noise analysis of 3D PDN in GDSII layouts which contain power/ground (P/G) TSV RC variation model. We explore the effect of TSV RC variation range, number of variation sources (P/G TSV count), number of C4 bumps and TSV size on the robustness of PDN under TSV RC variation. Our results show that TSV RC variations cause negligible influence on 3D PDN due to much smaller parasitic values of TSVs compared with that of entire PDN.

Keywords

integrated circuit noise; three-dimensional integrated circuits; 3D PDN; 3D power delivery network; C4 bumps; GDSII layout; TSV RC variation impact; TSV size; parasitic value; power supply noise; power-ground TSV RC variation model; through-silicon-via; Capacitance; Layout; Noise; Power supplies; Resistance; Three dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference and 2011 Materials for Advanced Metallization (IITC/MAM), 2011 IEEE International

Conference_Location

Dresden

ISSN

pending

Print_ISBN

978-1-4577-0503-8

Type

conf

DOI

10.1109/IITC.2011.5940325

Filename

5940325