Substrate noise optimization in early floorplanning for mixed signal SOCs

We propose a new approach to substrate noise reduction in early design planning of mixed-signal system-on-chip (MS-SOC). As typical in floorplanning, we assume that no detailed layout information is known for analog and digital blocks. Based on the physics of substrate noise phenomena and extensive noise simulations we propose to represent noise coupling as coupling between large-area (digital) and small-area (analog) substrate noise ports. A separation-dependent noise model for a lightly-doped substrate (preferable for mixed-signal designs) is derived. Our floorplanner reduces the overall noise and the number of analog blocks exceeding their noise limit. Experimental results on examples created from MCNC floorplanning benchmarks are very encouraging.