Directions in multiprocessor verification

IBM server products, mainframes and RISC engines, have witnessed an evolution in verification techniques. Costly special-purpose engines and blunt attempts to force operating system initial program load´s (IPL´s) in simulation have given way to the idea of more complete, lower level simulation with smart testcase generation algorithms. The idea is to explore the state space of the smaller piece of logic more fully before integrating if into its larger residence. This form of divide and conquer is being used in IBM´s Austin facility. Shared-Memory Multiprocessor (SMP) verification represents a special case of verification for an entire computer system. Many of its constraints are common with other parts of the system. This paper examines verification from a historical perspective, explores some of the ways of using existing hardware resources without additional capital investment and highlights how IBM´s Austin facility addresses SMP simulation