Investigation of local stress around TSVs by micro-Raman spectroscopy and finite element simulation

Stress concentration in through-silicon via (TSV) is studied by a calibrated micro-Raman spectroscopy (μRS) and correlated with numerical simulation. Results show that stress concentration is in transverse direction and it depends on the ratio of via diameter to via spacing. Further investigations on bended TSV lined with copper revealed that the stress level is lower than the one in TSV without copper. Chip-to-wafer 3D-stacking using microinserts thermocompression bonding shows that the 50 μm thick TSVs have negligible mechanical stress effect.