Investigation on MOCVD CoSi2 process for reduction of contact resistance at metal-silicon interface

A cobalt silicide process under various conditions on deposition of MOCVD Co and silicidation was investigated, and the best optimized condition of silicidation on physical profile and electrical performance of cobalt silicide in DRAM device has been suggested in this paper. We could obtained the best condition by statistical analysis of the physical profiles of CoSi₂ layer on blanket and patterned wafer with various conditions of CoSi₂ formation. CoSi₂ with different conditions of as-deposited cobalt thickness and 1^st RTA temperature was applied to 44nm device in order to evaluate contact resistance and junction BV. The improvement of contact resistance on N⁺ active silicon and N⁺/p junction BV with increase of cobalt thickness and decrease of 1^st RTA temperature was achieved. In addition, electrical performances on vertical gate memory device will be presented at this conference.