Title :
Treegion scheduling for wide issue processors
Author :
Havanki, William A. ; Banerjia, Sanjeev ; Conte, Thomas M.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
Instruction scheduling is one of the most important phases of compilation for high-performance processors. A compiler typically divides a program into multiple regions of code and then schedules each region. Many past efforts have focused on linear regions such as traces and superblocks. The linearity of these regions can limit speculation, leading to under-utilization of processor resources, especially on wide-issue machines. A type of non-linear region called a treegion is presented in this paper. The formation and scheduling of treegions takes into account multiple execution paths, and the larger scope of treegions allows more speculation, leading to higher utilization and better performance. Multiple scheduling heuristics for treegions are compared against scheduling for several types of linear regions. Empirical results illustrate that instruction scheduling using treegions treegion scheduling-holds promise. Treegion scheduling using the global weight heuristic outperforms the next highest performing region-superblocks by up to 20%
Keywords :
parallel architectures; processor scheduling; compilation; high-performance processors; instruction scheduling; linear regions; multiple execution paths; superblocks; traces; treegion; wide issue processors; Hardware; Linearity; Microprocessors; Parallel processing; Processor scheduling; Program processors; Tail; Topology; Tree data structures; Tree graphs;
Conference_Titel :
High-Performance Computer Architecture, 1998. Proceedings., 1998 Fourth International Symposium on
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-8186-8323-6
DOI :
10.1109/HPCA.1998.650566