DocumentCode
2010905
Title
Keynote address wednesday: Compute continuum and the nonlinear validation challenge
Author
Barton, John D.
Author_Institution
Platform Eng. Group, Intel Corp., Santa Clara, CA, USA
fYear
2013
fDate
6-13 Sept. 2013
Firstpage
9
Lastpage
9
Abstract
Summary form only given. Intel architecture scales from Exa-scale computing to hand-held and deeply embedded devices. A consistent architecture spanning many product domains brings benefits to silicon and product developers. But it also creates a validation challenge that is nonlinear in nature due to the differences in product complexity, use cases, and user expectations. In this talk, John will address how Intel views the reliability/resilience of large scale systems, how we test for user experience that might help users decide what is good for them, how we attempt to balance all the conflicting validation requirements in today´s rapidly evolving landscape spanning consumption devices with short life spans to enterprise applications with very high uptime and reliability expectations. In addition, he will comment on the developments in formal methods and their applicability to large-scale commercial validation/verification efforts.
Keywords
integrated circuit reliability; large-scale systems; Intel architecture; architecture spanning; compute continuum; embedded devices; exa-scale computing; formal methods; landscape spanning consumption devices; large scale system reliability; nonlinear validation challenge; product complexity;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2013 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Type
conf
DOI
10.1109/TEST.2013.6651872
Filename
6651872
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