Practical methods for extending ATE to 40 and 50Gbps

Author

Keezer, David C. ; Gray, Carl E. ; Te-Hui Chen ; Majid, A.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2013

fDate

6-13 Sept. 2013

Firstpage

1

Lastpage

10

Abstract

Practical techniques for generating test signals between 10Gbps and 50Gbps are described. An historical review shows that the problem of extending ATE to higher rates has been around for several decades, with ever-increasing speed requirements. We demonstrate, in this paper that multiplexing techniques that permitted 40-50 Mbps testing in the 1980s (then using 10-20MHz ATE) can be applied to the present problem of achieved 1000x faster rates today (40-50Gbps). Some intervening steps are shown that achieved 5-10Gbps, and recently 12-24Gbps. These are extended to demonstrate synthesis of signals between 40 and 50Gbps. The paper is intended to aid others who might face similar challenges in testing high-end products prior to the day when 50Gbps ATE becomes common-place.

Keywords

automatic test pattern generation; circuit testing; signal synthesis; ATE; bit rate 12 Gbit/s to 24 Gbit/s; bit rate 40 Gbit/s; bit rate 5 Gbit/s to 10 Gbit/s; bit rate 50 Gbit/s; frequency 10 MHz to 20 MHz; high-end product testing; high-speed digital test; signal synthesis; techniques; test signal generation; Field programmable gate arrays; Jitter; Logic gates; Multiplexing; Silicon germanium; Testing; Timing; ATE; High-Speed I/O; frequency-switching; high-speed digital test; jitter; multiplexing; picosecond; timing on-the-fly;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Type

conf

DOI

10.1109/TEST.2013.6651876

Filename

6651876