• DocumentCode
    2011229
  • Title

    From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware

  • Author

    Chen, Haibo ; Wu, Xi ; Yuan, Liwei ; Zang, Binyu ; Yew, Pen-Chung ; Chong, Frederic T.

  • Author_Institution
    Parallel Process. Inst., Fudan Univ., Shanghai
  • fYear
    2008
  • fDate
    21-25 June 2008
  • Firstpage
    401
  • Lastpage
    412
  • Abstract
    Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely degrade without hardware support for tracking taints. This paper observes that information flow tracking can be efficiently emulated using deferred exception tracking in microprocessors supporting speculative execution. Based on this observation, we propose SHIFT, a low-overhead, software-based dynamic information flow tracking system to detect a wide range of attacks. The key idea is to treat tainted state (describing untrusted data) as speculative state (describing deferred exceptions). SHIFT leverages existing architectural support for speculative execution to track tainted state in registers and needs to instrument only load and store instructions to track tainted state in memory using a bitmap, which results in significant performance advantages. Moreover, by decoupling mechanisms for taint tracking from security policies, SHIFT can detect a wide range of exploits, including high-level semantic attacks. We have implemented SHIFT using the Itanium processor, which has support for deferred exceptions, and by modifying GCC to instrument loads and stores. A security assessment shows that SHIFT can detect both low-level memory corruption exploits as well as high-level semantic attacks with no false positives. Performance measurements show that SHIFT incurs about 1% overhead for server applications. The performance slowdown for SPEC-INT2000 is 2.81X and 2.27X for tracking at byte-level and wordlevel respectively. Minor architectural improvements to the Itanium processor (adding three simple instructions) can reduce the performance slowdown down to 2.32X and 1.8X for byte-level and word-level tracking, respectively.
  • Keywords
    data flow analysis; exception handling; parallel architectures; parallel programming; security of data; decoupling mechanism; deferred exception tracking; load instruction; microprocessor; parallel architecture; security attack; software-based dynamic information flow tracking system; speculative hardware; store instruction; taint tracking; Application software; Computer science; Computer security; Hardware; Information security; Instruments; Measurement; Prototypes; Registers; Software prototyping; Deferred Exception; Dynamic Information Flow Tracking; Speculative Execution; Taint tracking;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2008. ISCA '08. 35th International Symposium on
  • Conference_Location
    Beijing
  • ISSN
    1063-6897
  • Print_ISBN
    978-0-7695-3174-8
  • Type

    conf

  • DOI
    10.1109/ISCA.2008.18
  • Filename
    4556743