Low power circuit techniques for fast carry-skip adders

A multi-level carry-skip addition scheme for static CMOS is presented which has O(lg n) asymptotic delay and has speed comparable to a carry-lookahead approach for typical operand bit precisions. However, the proposed architecture results in adders which dissipate nearly half the power of carry-lookahead adders. The proposed carry-skip method is also conflict free. This paper describes the proposed architecture and its circuit implementation, as well as the architecture´s asymptotic worst case delay analysis. Also, empirical results comparing the adder´s performance with other conventional architectures in a 0.5 μm CMOS process are provided