FITVS: A FPGA-Based Emulation Tool For High-Efficiency Hardness Evaluation

Author

Zheng, Hongchao ; Fan, Long ; Yue, Suge

Author_Institution

Beijing Microelectron. Technol. Inst., Beijing, China

fYear

2008

fDate

10-12 Dec. 2008

Firstpage

525

Lastpage

531

Abstract

This paper presents an improved tool called FITVS (Fault Injection Tool for Validating SEE) using the FPGA-based emulation system for fault grading. A novel library-replace-modeling technique that can quickly and easily perform SEE by injecting faults into the circuit nodes is proposed. It helps IC designers to enhance the quality of their design by providing the sensitivity information of all nodes. Also the fault injection effectiveness is improved with relative to the traditional methods by utilizing C# program and FPGA emulation, and the speed of injection can reach the order of lus/fault.

Keywords

C++ language; electronic design automation; field programmable gate arrays; integrated circuit reliability; C# program; FITVS; FPGA-based emulation tool; IC design; fault grading; fault injection tool for validating SEE; hardness evaluation; library-replace-modeling technique; single-event-effects; Automatic control; Circuit faults; Circuit simulation; Distributed processing; Emulation; Field programmable gate arrays; Hardware design languages; Libraries; Logic circuits; Very large scale integration; FPGA-based emulation; Fault Injection; Fault/Error Models; SEE;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing with Applications, 2008. ISPA '08. International Symposium on

Conference_Location

Sydney, NSW

Print_ISBN

978-0-7695-3471-8

Type

conf

DOI

10.1109/ISPA.2008.46

Filename

4725189