Title :
Adaptive testing - Cost reduction through test pattern sampling
Author :
Grady, Michael ; Pepper, Bradley ; Patch, Josh ; Degregorio, Michael ; Nigh, Phil
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.
Keywords :
cost reduction; logic circuits; logic testing; microprocessor chips; system-on-chip; IBM; SOC-ASIC; adaptive testing; cost reduction; logic circuit testing; processor; real-time analysis-optimization; test pattern sampling; wafer testing; Logic testing; Product design; Production; Program processors; Quality assessment; System-on-chip;
Conference_Titel :
Test Conference (ITC), 2013 IEEE International
Conference_Location :
Anaheim, CA
DOI :
10.1109/TEST.2013.6651891
