Soft Error Immune 180/spl mu/m/sup 2/ Sicos Upward Transistor Memory Cell Suitable for Ultra-High-Speed High-Density Bipolar Memories

Author

Idei, Y. ; Shiba, T. ; Homma, N. ; Yamaguchi, K. ; Nakamura, T. ; Onai, T. ; Namba, M. ; Tarnaki, Y. ; Sakurai, Y.

Author_Institution

Hitachi Device Engineering, Ltd., Japan

fYear

1991

fDate

28-30 May 1991

Firstpage

Lastpage

Keywords

Capacitance; Current measurement; Equivalent circuits; Log periodic antennas; Temperature dependence; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1991. Digest of Technical Papers., 1991 Symposium on

Conference_Location

Oiso, Japan

Type

DOI

10.1109/VLSIT.1991.705988

Filename

705988

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