Simulation of a simple loss/delay priority scheme for shared memory ATM fabrics

We report simulation results on the performance benefits associated with a mixed threshold-based loss priority and non-preemptive strict delay priority schedule for a shared memory ATM DMUX based on a hierarchically growable architecture. Good service discrimination between groups of CBR and VBR sources are achieved by using just a few levels of loss/delay priority service discriminators. The simulations, based on realistic traffic scenarios, indicate that loss priority thresholds combined with strict delay priority are simple, flexible, and resourceful cell handling scheme to be implemented in the first generation of ATM switches and multiplexers