Defect Tolerance Inspired by Artificial Evolution

Defect densities in integrated circuits are expected to increase as the semiconductor feature size decreases. Some form of transistor level defect tolerance is, therefore, desirable to reduce this increasing production challenge. Series and parallel replication of transistors can be applied to a circuit for tolerating stuck-open and stuck-closed transistors. The circuit is, however, still damaged by gate/drain and gate/source shorts. This paper applies an evolutionary algorithm to evolve a circuit tolerant to any single short between two transistor terminals. The evolved circuit is then analysed and a general defect tolerance technique is formed based on the evolved circuit. Applying the new technique to a circuit results in tolerance to any single stuck-open, stuck-closed, gate/drain shorted or gate/source shorted transistor. A Monte Carlo experiment compares the reliability of the new technique applied to a NAND gate with other redundant NAND gate implementations.