DocumentCode :
2011745
Title :
Reliability of n-Bit Nanotechnology Adder
Author :
Hanninen, Ismo ; Takala, Jarmo
Author_Institution :
Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere
fYear :
2008
fDate :
7-9 April 2008
Firstpage :
34
Lastpage :
39
Abstract :
The circuit technologies of the future are expected to have very high defect rates in the manufacturing process and also runtime faults, leading to paradigm shift toward design-for-reliability. There are various ways to increase the robustness of logic designs, but for many applications, the relations between the reliability of the complete system and the components are unknown, preventing justified design rulings. Previous work has analyzed the reliability of a full adder unit, establishing the expected failure rate via a decomposition of probabilistic transfer matrices of primitive gate level components. This paper extends the probabilistic analysis into a complete multi-bit ripple carry adder (RCA) unit, implemented on quantum-dot cellular automata nanotechnology. We show that the reliability of a RCA depends linearly on the failure rates of the macro level components (full adders and wire blocks), but the contributions are heavily weighted by the operand word length. Moreover, the reliability of the passive wiring grows to dominate the total reliability, while the full adders have smaller effect. This is actually very beneficial, since the wire blocks of a RCA can be easily hardened against defects; with reliable wiring, a large adder unit with 99% reliability level requires only relatively low 99.98% reliability from the full adder component.
Keywords :
adders; carry logic; failure analysis; integrated circuit reliability; logic design; matrix decomposition; nanoelectronics; quantum dots; circuit technology; design for reliability; expected failure rate; logic design robustness; macrolevel components; multibit ripple carry adder; n-bit nanotechnology adder reliability; operand word length; passive wiring; primitive gate level components; probabilistic analysis; probabilistic transfer matrix decomposition; quantum-dot cellular automata nanotechnology; wire blocks; Adders; Circuit faults; Failure analysis; Logic design; Manufacturing processes; Nanotechnology; Robustness; Runtime; Wire; Wiring; adder; arithmetic; nanotechnology; reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
Conference_Location :
Montpellier
Print_ISBN :
978-0-7695-3291-2
Electronic_ISBN :
978-0-7695-3170-0
Type :
conf
DOI :
10.1109/ISVLSI.2008.6
Filename :
4556766
Link To Document :
بازگشت