Title :
An efficient approach to pseudo-exhaustive test generation for BIST design
Author :
Chen, Chien-In H. ; Sobelman, Gerald E.
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computationally efficient and produces test generation circuitry with low hardware overhead is proposed. The effectiveness of this approach is demonstrated by detailed comparisons of its results with those that would be obtained by existing techniques
Keywords :
automatic testing; integrated circuit testing; logic testing; BIST design; built-in self-test; combinational circuit testing; hardware overhead; pseudo-exhaustive test generation; response analysis; test generation circuitry; Automatic testing; Built-in self-test; Circuit testing; Clustering algorithms; Hardware; Partitioning algorithms; Power engineering computing; Resource management; System testing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63431
