DocumentCode
2011892
Title
ELMMA: a new low power high-speed adder for RNS
Author
Patel, R.A. ; Benaissa, M. ; Powell, N. ; Boussakta, S.
Author_Institution
Dept. of Electron. & Electr. Eng., Univ. of Sheffield, UK
fYear
2004
fDate
13-15 Oct. 2004
Firstpage
95
Lastpage
100
Abstract
Modular adders are fundamental arithmetic components that are employed in residue number system (RNS) based digital signal processing (DSP) systems. They are widely used in modular multipliers, residue to binary converters and in implementing other arithmetic operations such as scaling. In addition, increasing operating frequencies, as well as a growing demand for portable electronics, have brought power reduction to the forefront of modern design methodologies. Thus, the design of power efficient modular adders is of great significance if RNS circuits are to be utilized in future DSP systems. We propose a new modular adder that is based on the ELM addition algorithm. VLSI implementations using 0.13 μm standard-cell technology show that the proposed architecture not only exhibits power efficiency, but also delay × area efficiency when compared to existing modular adder designs in the literature.
Keywords
VLSI; adders; digital signal processing chips; integrated circuit design; logic design; network synthesis; power consumption; residue number systems; 0.13 micron; DSP systems; RNS; VLSI implementations; arithmetic components; digital signal processing systems; high-speed adder; modular adders; modular multipliers; power reduction; residue number system; residue to binary converters; scaling; Adders; Circuits; Design methodology; Digital arithmetic; Digital signal processing; Frequency; Power dissipation; Signal processing algorithms; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on
Print_ISBN
0-7803-8504-7
Type
conf
DOI
10.1109/SIPS.2004.1363031
Filename
1363031
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