DocumentCode
2011969
Title
On the generation of compact test sets
Author
Kumar, Ajit ; Rajski, J. ; Reddy, S.M. ; Chen Wang
Author_Institution
Dept. of ECE, Univ. of Iowa, Iowa City, IA, USA
fYear
2013
fDate
6-13 Sept. 2013
Firstpage
1
Lastpage
10
Abstract
New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.
Keywords
VLSI; automatic test pattern generation; fault diagnosis; VLSI designs; compact test sets; fault propagation; industrial designs; line justification; test generation procedures; Automatic test pattern generation; Circuit faults; Compaction; Controllability; Logic gates; Observability; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference (ITC), 2013 IEEE International
Conference_Location
Anaheim, CA
ISSN
1089-3539
Type
conf
DOI
10.1109/TEST.2013.6651914
Filename
6651914
Link To Document