Title : 
A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures
         
        
            Author : 
Theocharides, Theocharis ; Michael, Maria K. ; Polycarpou, Marios ; Dingankar, Ajit
         
        
            Author_Institution : 
Dept. of Electr. & Comput. Eng., Cyprus Univ., Nicosia
         
        
        
        
        
        
            Abstract : 
Manycore architectures are expected to be the dominant trend in future general-purpose computing systems. With the number of on-chip processor cores rising to the hundreds, the problem of resource allocation cannot be addressed with traditional methods employed by off-chip multiprocessor architectures. We propose the use of system-level bidding-based algorithms as an efficient and real-time on-chip mechanism for resource allocation in manycore architectures. We simulate and evaluate the proposed bidding-based algorithms in a hierarchical, on-chip network connected manycore platform. Experimental results indicate performance improvement between 15-25%, when compared to an on-chip round robin allocation, while achieving a balanced workload distribution. The obtained results encourage further investigation of the applicability of such system-level algorithms for addressing additional important problems in manycore architectures.
         
        
            Keywords : 
computer architecture; resource allocation; manycore architectures; off-chip multiprocessor architectures; on-chip processor; resource allocation method; system-level bidding-based algorithms; Computer architecture; Engines; Hardware; Network-on-a-chip; Parallel processing; Real time systems; Resource management; Round robin; System-on-a-chip; Yarn; Chip Multiprocessors; Manycore Architectures; Networks on Chip; Resource Allocation;
         
        
        
        
            Conference_Titel : 
Symposium on VLSI, 2008. ISVLSI '08. IEEE Computer Society Annual
         
        
            Conference_Location : 
Montpellier
         
        
            Print_ISBN : 
978-0-7695-3291-2
         
        
            Electronic_ISBN : 
978-0-7695-3170-0
         
        
        
            DOI : 
10.1109/ISVLSI.2008.30