A SI-CMOS-MEMS process using back-side grinding

This paper presents a Si-CMOS-MEMS fabrication process which leaves the back-side silicon under the CMOS metal and oxide layers, and improves the uniformity of the back-side silicon using back-side grinding. The Si-CMOS-MEMS process includes a grinding process followed by a bonding process and conventional post-CMOS etch. A Si-CMOS-MEMS accelerometer is used to demonstrate the feasibility of the Si-CMOS-MEMS process. A 0.2 ¿m flatness of ground silicon surface over 2 mm length is achieved in this work. With this process, the measured sensitivity reaches 4.5 mV/g and ultra high flatness less than 0.05 ¿m out-of-plane variation of released accelerometers is achieved.